Title:
SIGNAL-GENERATING CIRCUIT
Document Type and Number:
Japanese Patent JP3563370
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a signal-generating circuit that realizes high noise immunity, low power consumption and a high-speed operation and satisfies eye pattern standard.
SOLUTION: An inverter circuit 11 inverts an input signal 101 and generates a 1st internal signal 104, and an inverter circuit 12 inverts the 1st internal signal 104 and generates a 2nd internal signal 105. A flip-flop 1 sets H level to an inversion signal 102 or a noninverting signal 103, when the 1st internal signal 104 or the 2nd internal signal 105 goes to H level. When the ON- resistance of a transistor(TR) Qn1 or Qn2 fluctuates caused by a manufacturing factor, an RC series circuit 2 or 3 controls the TR Qn1 or Qn2 to suppress fluctuations in the drive capability of the TR Qn1 or Qn2.
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Inventors:
Yasutaka Uenishi
Mikio Aoki
Mikio Aoki
Application Number:
JP2001173533A
Publication Date:
September 08, 2004
Filing Date:
June 08, 2001
Export Citation:
Assignee:
NEC Microsystems, Inc.
International Classes:
H03K5/151; H03K3/011; H03K3/356; H03K19/0185; (IPC1-7): H03K19/0185; H03K5/151
Domestic Patent References:
| JP2001006373A | ||||
| JP10190438A | ||||
| JP63133220A | ||||
| JP59016416A |
Attorney, Agent or Firm:
Kiyoshi Inagaki