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Patent Searching and Data


Title:
SIGNAL GENERATING CIRCUIT
Document Type and Number:
Japanese Patent JPH0494216
Kind Code:
A
Abstract:

PURPOSE: To obtain a signal whose duty ratio is 50% resulting from odd number frequency division of an input pulse signal by changing a level of an output signal as L, H, L,... at every an N (odd number)/2 period of the input pulse signal.

CONSTITUTION: An N-ary counter 2 is counted up every time an input signal is inputted sequentially, a carry-out signal CS is outputted therefrom when a desired odd number N is counted and the counter 2 is loaded and a signal outputted from an output terminal 2h is changed. An [(N+1)/2]-ary counter 8 is counted up at every input of the input signal CK sequentially and outputs a carry-out signal CS1 when the counter 8 counts a value being a quotient of an odd number (N+1) divided by 2 and the counter 8 is loaded. Then, an AND circuit 23 ANDs a signal S4 outputted from an inverting output terminal 20c of a 1st flip-flop 20 and a signal S5 outputted from an inverting output terminal 21c of a 2nd flip-flop 21. Thus, the signal whose duty ratio is 50% is obtained by applying odd number frequency division to the input signal.


Inventors:
MORIYA IKUKO
Application Number:
JP20926790A
Publication Date:
March 26, 1992
Filing Date:
August 09, 1990
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H03K23/00; (IPC1-7): H03K23/00
Attorney, Agent or Firm:
Matsumoto