Title:
SIGNAL GENERATION CIRCUIT FOR SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP3569863
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To generate many test-mode selection signals without increasing the number of pins by scrambling a first signal and a second signal which are output respectively from a prescribed number of buffers connected respectively to an n-th pin from a second pin, and high-voltage detection signals which are output respectively from the prescribed number of high-voltage detection means connected respectively to the n-th pin from the second pin, respectively.
SOLUTION: A buffer 32 and buffers 36-1 to 36-n buffer respective input signals Ai (where i=1 to n), and two kinds of signals PAiB, PAi (where i=1 to n) whose levels are mutually complementary are generated. High-voltage detectors 38-1 to 38-n generate signals SAi [where i=1 to (n-1)] when the respective input signals are high voltages. Scrambling circuits 40-1 to 40-n scramble the input signals PAiB, PAi (where i=1 to n) and the signals SAi [where i=1 to (n-1)], and signals PAiB, PPAi, SAj [where i=2 to n and j=1 to (n-1)] are generated.
Inventors:
Tetsuhiro Park
Ginger Na Tin
Choi Ken
Ginger Na Tin
Choi Ken
Application Number:
JP24033799A
Publication Date:
September 29, 2004
Filing Date:
August 26, 1999
Export Citation:
Assignee:
Samsung Electronics Co.,Ltd.
International Classes:
G01R31/28; G01R31/3181; G01R31/3185; G11C11/401; G11C11/407; G11C11/413; G11C29/14; G11C29/46; (IPC1-7): G11C29/00; G01R31/28; G01R31/3185; G11C11/401; G11C11/413
Domestic Patent References:
| JP2003145A | ||||
| JP3003189A | ||||
| JP3046193A | ||||
| JP6018629A | ||||
| JP10021698A |
Attorney, Agent or Firm:
Yasunori Otsuka
Kenichi Matsumoto
Kenichi Matsumoto
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