PURPOSE: To attain the reduction in an ununiformed part of an output signal with simple constitution by controlling a signal output based on the result of sum of signals with different delay time in a signal generator outputting a signal whose level is at an H level in M sets of unit periods and an L level in other periods in N sets of unit periods.

CONSTITUTION: Signals with a different delay time are formed by 6-stage of shift registers from a signal where a prescribed M sets (e.g., 6) of unit periods in N sets of unit periods goes to an H level, P sets (e.g., 4) of signals are outputted from the shift registers 4 at the 1st stage, 2nd stage, 5th stage and 6th stage, they are added by an adder circuit 5 to obtain 3-bit signals S0-S2. The signals and a 2-bit signal from a register 7 are added by an adder 6 to form 3-bit signals Z0-Z2, which are fed to a register 8. Then a low-order 2-bit is fed to a register 7, the number of the outputs of the adder 6 is less than P (e.g., 4), the 3-bit signals are outputted from the register 8 without any modification and when the number of the outputs of the adder 6 is 4 or over, an H level is outputted from the register 8 at the unit periods only, then the unniformed parts of H, L levels in the output signal are reduced and outputted with simple constitution.