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Patent Searching and Data


Title:
SIGNAL LEVEL ADJUSTING CIRCUIT
Document Type and Number:
Japanese Patent JPH04304085
Kind Code:
A
Abstract:

PURPOSE: To automatically adjust the sync chip level and deviation by only direct current control by eliminating the external resistance and without increas ing the number of pins.

CONSTITUTION: At the time of adjusting the carrier level of the current to be supplied to an FM modulation circuit 2, a video signal Vin is not, made to input in an emphasis circuit 3. A direct current signal S1 is inputted in a pin 10A and direct current I1 is adjusted. At the time when the Vin is not inputted, external reference current 12 flows from a voltage control amplifier 16 to a constant current source 15 and alternating current i does not flow to resistance R12. Internal reference voltage added to noninverted input of an operational amplifier OP 11 is added to a point P11. The voltage is given to a point 1 via an operational amplifier OP10 and resistance R10. The potential of a connection point P10 of a carrier adjusting circuit part I1 is calculated with the values of reference voltage kV, external reference current 11 and the resistance RIO which have no temperature characteristic. Current I equal to the external reference current 11 is supplied to the FM modulation circuit 2 from R10 via a transistor Q1 and the current I can easily be adjusted by a control signal S1 to be inputted in a terminal 10A.


Inventors:
YAMAGUCHI TSUGIO
Application Number:
JP9293891A
Publication Date:
October 27, 1992
Filing Date:
March 31, 1991
Export Citation:
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Assignee:
SONY CORP
International Classes:
H03G3/20; H04N5/91; H04N9/79; H04N9/793; H04N9/83; (IPC1-7): H03G3/20; H04N5/91; H04N9/79; H04N9/83
Attorney, Agent or Firm:
Kei Tanabe