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Title:
SIGNAL LEVEL DETECTING CIRCUIT
Document Type and Number:
Japanese Patent JPS60241327
Kind Code:
A
Abstract:

PURPOSE: To shorten the time spent in detection of fall of the signal level by detecting the fall of an AC input signal to a level lower than a prescribed level in accordance with the change of a smoothed signal.

CONSTITUTION: A signal (a) inputted to an input terminal 1 is subjected to full- wave rectification, and a high-level signal is outputted when the fall to a level lower than a prescribed level is detected by a level comparator 11. A pulse generator 12 outputs a high-level signal for only a certain period T when the signal of the level comparator 11 is switched from the low level to the high level, and the generator 12 outputs a low-level signal thereafter. This certain period T is set to a time longer than a half period of the input signal, and intervals of continuous pulses, which are generated when the input signal has a level higher than the certain level, are reduced to zero, and a full-wave rectified waveform (b) is converted equivalently to a smoothed waveform (c), and the fall of the input signal to a level lower than the prescribed level is detected by the change of this smoothed waveform (c).


Inventors:
YONEYAMA HISAKATSU
Application Number:
JP9641784A
Publication Date:
November 30, 1985
Filing Date:
May 16, 1984
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
H03F3/45; H03K5/08; H03K17/94; H04B17/00; H04B17/318; H04N5/94; (IPC1-7): H03F3/45; H03K17/94; H04B17/00; H04N5/94
Attorney, Agent or Firm:
Akio Takahashi



 
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