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Title:
SIGNAL NOISE ELIMINATING CIRCUIT
Document Type and Number:
Japanese Patent JPH06102293
Kind Code:
A
Abstract:

PURPOSE: To obtain a noise eliminating circuit which can deal with variation of the frequency band of noise contained in an input signal by simply modifying the operational conditions without requiring any modification Of compositional element.

CONSTITUTION: The signal noise eliminating circuit comprises a voltage/ frequency converter 5 receiving input signal, a counter 10 counting the number of pulses outputted from the voltage/frequency converter 5, a latch circuit 14 for latching the count of the counter 10 at a predetermined period, and a D/A converter 15 for converting the output from the latch circuit 14 into an analog value. Period of the latch circuit 14 is determined while taking account of the frequency of noise contained in the input signal.


Inventors:
MIYAZAKI YASUHIKO
TSUMURA TAKAHIRO
Application Number:
JP24792692A
Publication Date:
April 15, 1994
Filing Date:
September 17, 1992
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
G01R19/00; G01R19/252; H03M1/60; (IPC1-7): G01R19/00; G01R19/252
Attorney, Agent or Firm:
Takada Mamoru



 
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