To eliminate a defect of a spurious signal depending on an input to delta sigma (ΔΣ) modulation.
A fractional frequency divider 26 includes a latch 31 for latching frequency division data; a ΔΣ modulator 33; a digital dither circuit 32 that receives a digital input F denoting the fractional part of the frequency division data from the latch 31 and supplies a digital output alternately changed into F+k and F-k (k is an integer) or the input F itself to the ΔΣ modulator 33; and circuit means 34 to 38 for executing fractional frequency division based on an integer part (M value) of the frequency division data and an output of the ΔΣ modulator 33. When the ΔΣ modulator 33 receives a particular F value (e.g., F=2n-1), the digital dither circuit 32 can suppress the spurious signal caused as a result of quantization noise concentrated on a particular frequency and obtain a desired output frequency.
SAEKI TAKAHARU
Hiroshi Koyama
Hiroshi Takeuchi
Takahisa Shimada
Yuji Takeuchi
Katsumi Imae
Teshima Masaru
Atsushi Fujita
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