Title:
SIGNAL PROCESSING CIRCUIT HAVING VARIABLE GAIN INPUT STAGE
Document Type and Number:
Japanese Patent JP3530587
Kind Code:
B2
Abstract:
PURPOSE: To prevent the occurrence of disturbance of a signal by a transitional condition after variable gain is changed by correcting a value of a state variable so as to be in direct proportion to correction of an amplification/attenuation factor.
CONSTITUTION: A signal to be processed is supplied to input of a first variable gain stage 4 to perform amplification/attenuation by a line 10, and the stage 4 sends out an amplitude-standardized signal to a line 12 as output in response to an inputted signal. The stage 4 is controlled by a gain control means 6. A signal processing circuit 2 sends out a processed signal to a line 14 as output. A line 16 adds a signal supplied from the processing circuit 2 to the gain control means 6 so as to change gain of the stage 4. Two lines 18 and 20 respectively supply control signals to the stages 4 and 8. The stages 4 and 8 respectively change its gain in response to these. That is, a value of a state variable is corrected so as to be in direct proportion to correction of an amplification/ attenuation factor, and a transitional condition is restrained.
Inventors:
Nys, Olivier
Enrique, Marcelo Blumenkrantz
Enrique, Marcelo Blumenkrantz
Application Number:
JP16751194A
Publication Date:
May 24, 2004
Filing Date:
June 28, 1994
Export Citation:
Assignee:
CSEM CENTRE SUISSE ELECTRON & DE MICROTECH SA RECH & DEV
International Classes:
G01R19/00; H03G3/00; G01R15/08; H03H19/00; H03K7/06; H03M3/02; H03M3/04; (IPC1-7): G01R15/08; H03M3/04
Attorney, Agent or Firm:
山川 政樹