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Patent Searching and Data


Title:
SIGNAL PROCESSING CIRCUIT AND SIGNAL PROCESSING METHOD
Document Type and Number:
Japanese Patent JPH11284671
Kind Code:
A
Abstract:

To enable a highly reliable serial transmission at a low cost with a small circuit scale by preventing multistage propagation of a pathological signal (pattern data with maximum component, etc.), and minimizing a cumulative increase of jitters in the multistage relaying.

A repeater 160 supplies data Din transmitted by a coaxial cable to an equalizer 161 to compensate attenuation characteristics and then a D flip-flop 163 latches the data by using a serial clock signal SCK reproduced from the data Din to obtain reception data RSD. The reception data RSD is converted by a converter 164 from an NRZI(non-return-to-zero inverted) code to an NRZ(non-return-to zero) code and descrambled by a descrambler 165 to obtain serial digital data SDr. The data SDr is scrambled by a scrambler 166 and further converted by a converter 167 from the NRZ code to the NRZZI code to obtain data Dout to be resent, so that the data Dout is sent out to the coaxial cable through a cable driver 168.


Inventors:
MUNAKATA ICHIRO
Application Number:
JP8660498A
Publication Date:
October 15, 1999
Filing Date:
March 31, 1998
Export Citation:
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Assignee:
SONY CORP
International Classes:
H03M5/06; H03M5/12; H04J3/00; H04J3/08; H04L7/00; H04L25/52; H04N7/16; H04N7/167; H04N21/647; (IPC1-7): H04L25/52; H03M5/06; H04J3/00; H04J3/08; H04L7/00; H04N7/16; H04N7/167
Attorney, Agent or Firm:
Kunio Yamaguchi (1 person outside)