To realize mute processing to an invalid signal input and that to a decode disable data by a simple circuit configuration and through exactly the same processing flow.
When a track buffer 2 is an empty state, and/or a data read from the track buffer 2 is halted by a read control signal 12, the signal processing circuit is configured so as to change over an input data 14 of an audio processing circuit 8 to a fixed value by a selector 15. With this configuration, the audio processing circuit 8 is brought into the state in which a synchronous signal is undetectable as long as the input data is the fixed value, and processing such as muting can be carried out by exactly the same processing as that in the case that the input data itself is decode disable data.
MATSUI KIYOKATSU
SOGABE TOMOKO
