To provide a signal processing filter system that can decide between setting the reduction in a signal throughput total sum as a higher priority or the reduction in a signal processing delay time as a higher priority and can cope with both.
A Fourier transform section 10, a frequency domain echo cancelation control filter section 30, and an inverse Fourier transform section 40 configure a filter module in the frequency domain, and a time domain echo cancelation control filter section 50 configures a filter module of the time domain. A switch section 75 switches 1st switch sections 70-73 to configure a domain selectable signal processing filter module. When 2nd switch sections 60, 61 use a noise suppression control filter section 20, the signal throughput reduction takes precedence over the signal processing delay time reduction to select the frequency domain filter module, and when the 2nd switch sections 60, 61 use no noise suppression control filter section 20, the signal processing delay time reduction takes precedence over the signal throughput reduction to select the time domain filter module.
JP2022011894 | NOISE REDUCTION CIRCUIT |
WO/2003/001173 | A NOISE-STRIPPING DEVICE |
JPH02244096 | VOICE RECOGNIZING DEVICE |
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JPH09148965A | 1997-06-06 | |||
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