SIGNAL PROCESSING UNIT/METHOD AND MEMORY STORAGE METHOD

Japanese Patent JP3825888

B2

PROBLEM TO BE SOLVED: To allow a single memory means to conduct each processing by arranging data in the memory means according to processing sequence and processing units and storing another data not being processing objects to an idle area of the memory. SOLUTION: A clock whose frequency is e.g. 27.6MHz is fed from an external frequency oscillator 27 to a frequency multiplier 29, from which a multiplied 67.6MHz signal is supplied as a reference clock. The 67.6MHz reference clock signal is selected to be an integer multiple of the signal 13.5MHz locked to a horizontal synchronizing signal generated from a frequency oscillator 31. Then each memory array in a memory 17 is made up of a sense amplifier provided independently of the memory cell and data of a prescribed amount stored in the sense amplifier are burst-transferred synchronously with the clock so as to set the transfer speed to the outside of the memory and the operating speed in the internal bank independently and a high speed read/write access is attained as a whole.