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Title:
信号処理方法、信号処理装置、信号処理デバイスおよびコンピュータ記憶媒体
Document Type and Number:
Japanese Patent JP7267424
Kind Code:
B2
Abstract:
Disclosed are a signal processing method, apparatus, device, and computer storage medium, said method comprising: obtaining clock recovery input data; performing frequency-domain clock recovery on the clock recovery input data to obtain clock recovery output data; according to said clock recovery output data, performing frequency-domain blind equalization to obtain frequency domain balance data.

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Inventors:
Kano Sohei
Application Number:
JP2021531472A
Publication Date:
May 01, 2023
Filing Date:
December 18, 2019
Export Citation:
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Assignee:
Thane Chips Technology Company Limited
International Classes:
H04B10/61; G06F17/10; H03H17/02; H04B10/2569; H04L7/027; H04L27/01
Domestic Patent References:
JP2017503446A
JP2018195925A
JP2016208115A
Attorney, Agent or Firm:
Hideki Miyata
Hiroaki Sakai



 
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