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Title:
SIGNAL PROCESSOR FOR PCM SIGNAL
Document Type and Number:
Japanese Patent JPS5760508
Kind Code:
A
Abstract:

PURPOSE: To perform excellent signal processing without malfunction, even if the transfer rate of input and output data is different, by alternate write-in and readout operations of two systems of memories.

CONSTITUTION: Since the write-in of an input data 1 to a memory 29 can be made from around the start of the next horizontal synchronizing period with synchronized state to the output data master block via auxiliary memories 8, 9, even if the length of the horizontal synchronizing section is reduced because of missing of signals and skew, the signal processing can be made with sufficient time margin. This, the transfer route of the input data 1 and output data can arbitrarily be set and the processing as to correction can be made in synchronizing with the output data master block, allowing to reduce the production of malfunction even with variation in the transfer route of the input data 1.


Inventors:
HIBINO CHITOSHI
KOBAYASHI MASAHARU
YAMAZAKI SHIGERU
ARAI TAKAO
Application Number:
JP13382980A
Publication Date:
April 12, 1982
Filing Date:
September 26, 1980
Export Citation:
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Assignee:
VICTOR COMPANY OF JAPAN
HITACHI LTD
International Classes:
H03M7/00; G11B20/10; G11B20/18; H04L7/00; H04L13/08; (IPC1-7): G11B5/09; H04L7/00; H04L13/08
Domestic Patent References:
JPS5466815A1979-05-29