To provide a signal processor capable of generating a clock signal whose duty cycle is approximate 50% in accordance with an input signal rate with a simple circuit configuration.
By using an input clock signal obtained when a serial signal in burst mode is converted into a parallel signal and effective data identification pulse, the number of clocks of the input clock signals is counted from an input timing of the valid data identification pulse to the next input timing of the valid data identification pulse, a half value of the count rate is obtained by a multiplier 145 and the half value is compared with the count value of a counter 142 by a comparator 146. On the basis of the comparison result, an output clock signal is generated which rises in almost a half cycle or falls in almost a half cycle of the valid data identification pulse cycle in an FF circuit 143.
Satoshi Kono
Makoto Nakamura
Kurata Masatoshi
Takashi Mine
Yoshihiro Fukuhara
Sadao Muramatsu
Ryo Hashimoto
Next Patent: PORTABLE TERMINAL AND DATA COLLECTION METHOD