Title:
SIGNAL PROCESSOR
Document Type and Number:
Japanese Patent JP2023104272
Kind Code:
A
Abstract:
To provide a compact device with a reduced circuit scale.SOLUTION: In processing baseband signals output from first low-pass filters 5A, 5B, a first multiplier 62A multiplies baseband signals with in-phase components and in-phase local oscillation signals to generate and output quadrature modulation high-frequency signals with in-phase components, and a second multiplier 62B multiplies baseband signals with quadrature components and quadrature-phase local oscillation signals to generate and output quadrature modulation high-frequency signals with quadrature-components. In processing high-frequency signals output from an amplifier 7, the first multiplier 62A multiples high-frequency signals and in-phase local oscillation signals to generate quadrature demodulation baseband signals with in-phase components, to be output to the first low-pass filter 5A, and the second multiplier 62B multiples high-frequency signals and quadrature-phase local oscillation signals to generate quadrature demodulation baseband signals with quadrature components, to be output to the second low-pass filter 5B.SELECTED DRAWING: Figure 1
Inventors:
ARAI SAKAE
Application Number:
JP2022005154A
Publication Date:
July 28, 2023
Filing Date:
January 17, 2022
Export Citation:
Assignee:
JAPAN RADIO CO LTD
International Classes:
H04L27/36; H04B1/40; H04L27/38
Attorney, Agent or Firm:
Narutokirou Harashima
Kazuhiko Satoh
Kazuhiko Satoh
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