PURPOSE: To provide a signal processor where a high synchronization characteristic which is held by a hardware interruption processing is kept as it is and also a sufficient noise proofing characteristic is also possessed.

CONSTITUTION: A signal A outputted from the REM terminal of a high-order CPU which is not shown in a figure is inputted to the interruption port INT of a signal driving control CPU and to a normal input port Pi respectively as the signals B and C. Timers x and y are started simultaneously at the time of the rising of the interrupting signal B, the timer y is counted-up before time X which is set by the timer x and it is judged whether or not the signal of the port Pi is equal to the signal B of the port INT. The signal C is adopted as the normal input signal at the time of equality and a pulse signal is outputted from the terminals P0-P3 after time X elapses. The pulse signal is not outputted at the time of difference.