PURPOSE: to read a desired time division frame among stored signals by applying independently write of a signal possible for change in the unit of time division frame and read of the stored signal.

CONSTITUTION: A counter circuit 1 is initialized by a multi-frame time division frame time division frame synchronizing signal MFS, counts a time division frame synchronizing signal FS to form write address information ADδ1 of storage circutis 7, 8 storing a signal DA1 changing it in the unit of time division frame by storage circuits 7, 8. the count circuit 2 is initialized by the control signal CT1 from the output side B, counts the control signal CT2 to form read address information AD2 of the circuits 7, 8. A selection signal SL from an FF5 using the signal MFS as a toggle signal repeats 1, 0 at each multiple time division frame. When the level of the signal SL is logical 1, a selection circuit 3 selects the information AD1, the circuit 7 writes the signal DA1, the selection circuit 4 selects the information AD2, the circuit 8 is brought into the read state and the signal DA2 is outputted to the B side. When the signal SL is logical 0, the circuit 7 is in read state and the circuit 8 is in the write state.