Title:
SIGNAL PROCESSOR
Document Type and Number:
Japanese Patent JPS6476460
Kind Code:
A
Abstract:
PURPOSE:To decrease a noise component by separating a first frequency component to be attenuated with prescribed quantity and a second frequency component to be different from the frequency, adding the first and second frequency components and amplifying a third frequency component to this signal. CONSTITUTION:For an input luminance signal, a low frequency component is extracted in an LPF100a and the signal is outputted to the + terminal of an adder 100b. On the other hand, the luminance signal is multiplied by a coefficient multiplying circuit 100c and the whole level of the signal is suppressed. Then, a high frequency component is extracted by an HPF100d. After that, the signal is supplied to a non-linear converting circuit 100e and a signal to be smaller than a prescribed amplitude is outputted as it is. Then, a signal to be larger than the prescribed amplitude is successively suppressed and supplied to the + terminal of the adder 100b. Thus, since the adder is composed of the low frequency component from the LPF and the high frequency component to be non-linear conversion-processed from the circuit 100e and these components are added, the signal, whose high frequency component is suppressed with the prescribed quantity, is outputted. Further, by loading emphasis to this output, the noise component can be decreased.
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Inventors:
FUJIMOTO MAKOTO
MIMURA TOSHIHIKO
MIMURA TOSHIHIKO
Application Number:
JP23317387A
Publication Date:
March 22, 1989
Filing Date:
September 16, 1987
Export Citation:
Assignee:
CANON KK
International Classes:
H04N5/922; G11B20/06; H04N5/92; (IPC1-7): G11B20/06; H04N5/92
Domestic Patent References:
| JPS5942369A | 1984-03-08 |
Attorney, Agent or Firm:
Marushima Giichi