Title:
SIGNAL RECEIVER
Document Type and Number:
Japanese Patent JP3404792
Kind Code:
B2
Abstract:
PURPOSE: To output correct data within an optimum time by applying proper muting or mute release in response to the operating mode.
CONSTITUTION: A tuner 3 selects an RF signal of a band in RF signals subjected to frequency multiplex and converts the signal into an IF signal. A demodulation circuit 4 demodulates the IF signal to output serial data. A demultiplexer 5 demultiplexes time division multiplexing to extract data of one frame and applies error correction decoding and to extract an audio channel and a data channel. An expansion circuit 6 implements expansion processing and volume processing. A microprocessor discriminates the operating mode of the receiver and controls variably a discrimination period of muting or mute-releasing of an output signal, that is, a count time of an error flag from the demultiplexer 5.
Inventors:
Katsutoshi Hirayasu
Application Number:
JP6337093A
Publication Date:
May 12, 2003
Filing Date:
February 27, 1993
Export Citation:
Assignee:
ソニー株式会社
International Classes:
H04B1/10; H04B14/04; H04L1/00; (IPC1-7): H04B14/04; H04B1/10; H04L1/00
Domestic Patent References:
| JP3182134A | ||||
| JP62279715A | ||||
| JP62266935A | ||||
| JP58139310A | ||||
| JP57133508A |
Attorney, Agent or Firm:
Akira Koike (2 outside)
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