PURPOSE: To make highly efficient signal receiving possible even when disturbance of short time or the state of no signal is generated by maintaining the state of signal receiving when time interval between a time component signal and next time component signal during signal receiving is within a specific time range.

CONSTITUTION: T2∼T4 out of output of a shift register 4 are connected to input of an OR circuit 5, and a time signal T is obtained by the OR circuit 5. The output period of the time signal T is made a specified time, and the specific time is determined by the number of bits of the shift register 4 and selection of bits. An AND circuit 9 is a no-signal state detecting circuit having function to prohibit outputting of a reset signal in the limits of specific time regardless of presence or absence of a time component signal RxC and outputs a reset signal of JKFF 10 detecting absence of the time component signal RxC when the specific time is exceeded.