Title:
SIGNAL SUPPRESSING DEVICE
Document Type and Number:
Japanese Patent JPH02198066
Kind Code:
A
Abstract:
PURPOSE:To obtain different signal suppression from the transient state such as application of shock noise in the operation of a mechanism button and from the steady-state by applying a DC bias and an AC bias simultaneously in parallel with a base of a transistor (TR). CONSTITUTION:A DC bias circuit comprising a resistor R2 and an AC bias circuit comprising C1, R4, D1, C2 and R3 being also components of a DC cut circuit and a rectifier circuit are added in parallel with a base of a TR. A leaf switch SW 1 is turned off to detect it that a head is detached from a tape at the mechanism operation such as PLAY STOP button operation change, for example, and a voltage VB is applied simultaneously to both the DC bias circuit and the AC bias circuit connecting to the base of the TR. Thus, a large signal suppression is attained in the transient state and only a DC bias is applied in the steady-state thereby obtaining different signal suppression.
Inventors:
MATSUOKA OSAMU
Application Number:
JP1541389A
Publication Date:
August 06, 1990
Filing Date:
January 25, 1989
Export Citation:
Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
G11B20/02; (IPC1-7): G11B20/02
Attorney, Agent or Firm:
Shigetaka Awano (1 person outside)
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