SIGNAL SYNTHESIS CIRCUIT

Japanese Patent JPH01114120

A

PURPOSE:To improve the degree of circuit integration of a semiconductor integrated circuit by providing a logic circuit synthesizing an output signal of a synchronizing frequency divider circuit not inputted to a Schmitt circuit and an output of the Schmitt circuit so as to reduce number of components. CONSTITUTION:Output signals A, B, C of the synchronizing frequency divider circuit 1 synchronize with a clock CLK and the signals B, C are inputted respectively to Schmitt circuits 3, 4 respectively. Then output signals B1, C1 of the circuits 3, 4 and the output signal A of the circuit 1 are given to an OR circuit 2, which synthesizes input signals to output a synthesis signal X. Since the trailing of the waveform of the signals B1, C1 is retarded at times t1, t2 having a possibility of hazard (unstable phenomenon of logical operation in leading/ trailing timing of pulse signal) with respect to the leading of the waveform of the signal A, no hazard takes place. Thus, an excellent output signal is obtained by using circuits 3, 4 comprising two transistors in place of a conventional D-FF and number of components is halved or lower than a conventional number of components, then the circuit integration of the semiconductor integrated circuit is improved.

JPS54128253	FREQUENCY SYNTHESIZING CIRCUIT
JP5187618	Counter device
JP4383876	High-speed programmable divider with synchronous reload

AMANO KAORI

JP27221487A

May 02, 1989

October 27, 1987

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NEC CORP

H03K23/64; H03K5/08; H03K5/1252; H03K23/40; (IPC1-7): H03K23/40

JPS5034448A	1975-04-02
JPS52157744U	1977-11-30
JPS57204740U	1982-12-27
JPS4858763A	1973-08-17
JPS4920507U	1974-02-21
JPS60223227A	1985-11-07

Naoki Kyomoto (2 outside)

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