PURPOSE: To relieve the load of provision for circuits for timing control, delay equalization and timing introduction by providing a programmable timing delay unit to control a signal timing to a signal processing circuit to each of signal processing units connected in cascade.
CONSTITUTION: Signal processing circuits 26 connected in cascade receive an input signal from a signal routing switcher, process the received signal and returns the processed signal to the signal routing switcher. The signal timing in the signal processing circuits 26 is controlled by a programmable timing delay unit 28. The delay unit 28 receives a reference signal 30, a clock pulse 31 and a timing deviation signal 32 from a central timing unit via a timing control signal interface 16, and advances and controls the signal timing in the signal, processing circuit 26 by using the signals 31, 32, 33. Thus, the digital output signal is generated in a prescribed constant timing with respect to the external reference signal.
MAIKERU PORATONITSUKU
ANDORIYUU RAARII
