Title:
SILCON WAFER AND METHOD FOR EVALUATING ITS SURFACE ROUGHNESS
Document Type and Number:
Japanese Patent JP3906577
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a silicon wafer that is superior in releasing property in electrostatic chuck and in which no generation or adhesion of particles occur and to realize its evaluation standard and evaluation method, when the surface condition of wafer after etching is evaluated.
SOLUTION: This silicon wafer is provided with one main plane which is mirror-surface polished, and a silicon abundance ratio at a rate of 5% or lower in a depth of 100 nm from the main surface of unpolished, while its abundance ratio is 50% or higher at a depth of 1 μm from the surface. This evaluation method is used to measure the surface roughness of a silcon wafer and find out the baring curve at the desired depth based on the measured result, so as to evaluate the surface roughness.
Inventors:
Hitoshi Kakuda
Rikako Yanagisawa
Uchiyama Yuu
Tonohiko Mizuno
Rikako Yanagisawa
Uchiyama Yuu
Tonohiko Mizuno
Application Number:
JP22933698A
Publication Date:
April 18, 2007
Filing Date:
July 30, 1998
Export Citation:
Assignee:
Shin-Etsu Semiconductor Co., Ltd.
International Classes:
G01B21/30; H01L21/02; G01N37/00; G01Q30/04; G01Q60/24; H01L21/66; H01L21/677; (IPC1-7): H01L21/02; G01B21/30; H01L21/66; //G01N13/16
Domestic Patent References:
JP9079840A | ||||
JP8160058A | ||||
JP6349795A | ||||
JP9293774A | ||||
JP9097775A | ||||
JP8017777A | ||||
JP7235534A | ||||
JP2222534A |
Attorney, Agent or Firm:
Mikio Yoshimiya