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Patent Searching and Data


Title:
SIMPLIFIED FAULT SIMULATION SYSTEM
Document Type and Number:
Japanese Patent JPH04184681
Kind Code:
A
Abstract:

PURPOSE: To perform the diagnosis of a fault appropriately by eliminating indefinite transient phenomenon by storing the state transition data of the output value of each logic gate and eliminating an event within designated time width in simplified simulation for a circuit.

CONSTITUTION: The state change of the logic gates MA-ME in circuit information are performed, and the patterns of them are stored. Thence, the time width 10 is designated, and the events MC, MD, and ME with indefinite state are eliminated. It is detected whether or not the logic gates are operated as 1→0 or 0→1 by an input pattern, and when the state change such as 1→0, 0→1 occurs, it is assumed that the logic gate is operated. It is assumed that the logic gate MA is operated necessarily. It is decided that the logic gate MB is not operated by only the operation of 0→1, and the logic gate MC from which '6' is deleted and is not operated by only the operation of 1→0, and the logic gate MD from which '4' and '6' are deleted and is operated since change 1→0→1 occurs, and the logic gate ME is operated by eliminating '8'. Thereby, the simplified fault simulation can be accurately performed.


Inventors:
WAKAMATSU EMI
Application Number:
JP31533990A
Publication Date:
July 01, 1992
Filing Date:
November 20, 1990
Export Citation:
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Assignee:
NEC CORP
International Classes:
G06F17/50; G01R31/28; (IPC1-7): G06F15/60
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)