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Patent Searching and Data


Title:
SIMULATION DEVICE
Document Type and Number:
Japanese Patent JPH05108752
Kind Code:
A
Abstract:

PURPOSE: To perform a delay simulation which is closer to the operation of an actual device by calculating a wiring delay for which on and off states of a transfer gate are considered.

CONSTITUTION: Input data and input patterns are fetched and a gate output terminal extracting means 103 extracts a gate output terminal based on the converted internal data. Then, a connection relation retrieving means 104 retrieves a connection relation, while considering whether a transfer gate in connected or not for the extracted terminal. A delay calculating means 105 calculates the delay by classifying into a case where the transfer gate is connected and a case where it is not connected by using the retrieval result. Thus, a simulation is executed based on the prepared internal data and the result is preserved. Thus, since the delay time can be calculated by considering the on/off of the transfer gate, an error can be reduced.


Inventors:
SAGAYAMA HIDEKI
Application Number:
JP26795391A
Publication Date:
April 30, 1993
Filing Date:
October 16, 1991
Export Citation:
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Assignee:
NEC CORP
International Classes:
G06F11/25; G06F11/26; G06F17/50; (IPC1-7): G06F11/26; G06F15/60
Attorney, Agent or Firm:
Naotaka Ide