Title:
SIMULATION METHOD, SIMULATION DEVICE AND STORAGE MEDIUM FOR STORING SIMULATION PROGRAM
Document Type and Number:
Japanese Patent JP3147851
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To have even processing an execution time of which is different every time it is executed simulated at high speed with precision and also to have interruption performed during executing routine processing simulated.
SOLUTION: This simulation method successively executes feasible native version typical processing 231 to 23n without having a simulation means 24 interpret, an atypical processing simulation means 25 interprets plural instructions composing atypical processing one by one whose inspection is not completed and executes them. A host time counting means 30 counts the first time immediately before the native version typical processing is executed or is completed and the second time immediately before the execution is completed or interrupted by interruption on the basis of a coefficient α for indicating a performance difference between a target CPU and a host CPU. A target time counting means 27 counts a target time which the target CPU needs to execute a target program on the basis of the first and the second times and the coefficient α.
Inventors:
Kazuya Hashimoto
Application Number:
JP8101098A
Publication Date:
March 19, 2001
Filing Date:
March 27, 1998
Export Citation:
Assignee:
NEC
International Classes:
G06F11/28; G06F9/455; G06F11/22; G06F11/26; G06F11/34; (IPC1-7): G06F11/26
Domestic Patent References:
| JP6250874A | ||||
| JP6324883A | ||||
| JP7160537A |
Attorney, Agent or Firm:
Yukio Nishimura