Title:
シングルキャリア・マルチキャリア無線アーキテクチャ
Document Type and Number:
Japanese Patent JP2005528002
Kind Code:
A
Abstract:
A Baseband receiver including a CIR estimate block, gain, phase and timing loops, a CMF, a single-carrier processor and a multi-carrier processor. The CIR estimate block generates an impulse response signal based on a receive signal that is a single-carrier signal or a single-carrier segment of a mixed carrier signal. The single-carrier segment has a spectrum that approximates a multi-carrier spectrum. The gain, phase and timing loops adjust gain, phase, frequency and timing to provide an adjusted receive signal. The CMF filters the adjusted receive signal according to the impulse response signal. The single-carrier processor processes the adjusted and filtered receive signal to resolve a single-carrier segment of a mixed carrier signal. The single-carrier processor detects a mixed carrier mode indication in a single-carrier segment and asserts a start indication. The multi-carrier processor processes a multi-carrier segment of a mixed carrier signal in response to assertion of the start indication.
Inventors:
Webster, Mark A
Shields, Michael Jay
Shields, Michael Jay
Application Number:
JP2003531706A
Publication Date:
September 15, 2005
Filing Date:
September 25, 2002
Export Citation:
Assignee:
Intersil Americas Inc.
International Classes:
H04J11/00; H04B7/08; H04L12/28; H04L12/56; H04L25/02; H04L27/00; H04L27/26; (IPC1-7): H04J11/00; H04B7/08
Attorney, Agent or Firm:
Tadahiko Ito
Shinsuke Onuki
Tadashige Ito
Naoki Fujimura
Shinsuke Onuki
Tadashige Ito
Naoki Fujimura