PURPOSE: To facilitate the utilization of a built-in RAM and the exchange of data between register banks.
CONSTITUTION: A central processing unit (CPU) 2 is equipped with a data memory RG to output internal data used as a general-purpose register to an exclusive data bus SDBUS while being connected to the exclusive data bus SDBUS, which transfers data by connecting built-in RAMs, and a bank address bus BABUS to transfer address information corresponding to data transferred by the exclusive data bus SDBUS by connecting the CPU 2 and the built-in RAM, and a bank instruction register BP to hold the position information of a mapping area in the case of mapping the contents of the data memory RF into the built-in RAM and to output the information to the bank address bus BABUS. The built-in RAM is equipped with a bank address control circuit to generate a real address based on the contents of the bank instruction register BP and a selecting circuit to select either the real address generated by the bank address control circuit or an address on a source address bus.
OGAWA SUNAO
YAMADA YASUO
KANUMA AKIYOSHI
