Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
SINGLE CHIP MICROCOMPUTER
Document Type and Number:
Japanese Patent JPS62260261
Kind Code:
A
Abstract:
PURPOSE:To correctly read out a ROM by using plural system clocks. CONSTITUTION:The 1st and 2nd system clock generating circuits 1 and 2 produce the 1st and 2nd system clocks 3 and 4 respectively after receiving the output of a basic clock. A system clock selection circuit 5 receives both clocks 3 and 4 and selects one of these two clocks in response to the frequency of the basic clock to output it. Then the ROM 7 of a dynamic action is precharged by the timing of a selected system clock 6 and the ROM output data 8 is read out and latched by a ROM output data latch 9. The latch 9 outputs data to a data bus by the timing of the clock 3 regardless of the frequency of the basic clock.

Inventors:
KUMAGAI TOSHIYUKI
Application Number:
JP10535286A
Publication Date:
November 12, 1987
Filing Date:
May 07, 1986
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
NEC CORP
International Classes:
G11C17/00; G06F1/04; G06F1/08; G06F15/78; (IPC1-7): G06F1/04; G06F15/06; G11C17/00
Attorney, Agent or Firm:
Uchihara Shin



 
Previous Patent: SECURITY SYSTEM

Next Patent: DATA TRANSFER CONTROLLER