Title:
SINGLE CHIP MICROCOMPUTER
Document Type and Number:
Japanese Patent JPS6431255
Kind Code:
A
Abstract:
PURPOSE:To suppress the propagation of an abnormal signal after the holding time of a dynamic circuit by adding a circuit for detecting a sampling time and generating a signal longer than the sampling time of a memory to the program memory. CONSTITUTION:A latch signal generating part for latching the output signal of the program memory 4 and a latch circuit 34 are integrated on the base of a single semiconductor, so that the titled microcomputer is constituted. The program memory 4 is precharged and dynamically read synchronously with a signal from a clock generating part 2. Then, the latch signal generating part generates the latch signal of a pulse duration longer than the sampling time of the memory 4 synchronously with a signal from the clock generating part 2 to store and hold the output of the memory 4 of a normal sampling state at that time in the latch circuit 34 and supply to the respective required parts of a device from the latch circuit 34. Thereby, the propagation of the signal of an abnormal value is suppressed and the device can be constantly operated based on a normal signal.
Inventors:
AKASHI MINEO
Application Number:
JP18910587A
Publication Date:
February 01, 1989
Filing Date:
July 28, 1987
Export Citation:
Assignee:
NEC CORP
International Classes:
G11C11/41; G06F15/78; G11C11/34; (IPC1-7): G06F15/06; G11C11/34
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)