Title:
SLOT SYNCHRONIZING METHOD
Document Type and Number:
Japanese Patent JP2715873
Kind Code:
B2
Abstract:
PURPOSE: To miniaturize a transmitter/receiver and to reduce cost by preventing the increase of the peak factor of a transmission carrier due to the centralization of synchronizing symbols having the maximum amplitude shift amount of each sub-carrier in a time division multiplexing digital communication system used jointly with frequency division multiplexing.
CONSTITUTION: A transmitter divides the bit string of a digital signal into plural bit strings, performs separate amplitude phase shift modulation for plural subcarriers SC 1 to SC 4 which are different in frequencies with each other by each prescribed bit number units, symbolizes the subcarriers and transmits the subcarriers by a communication slot unit alloted commonly. At this time, a communication slot 101 and plural symbols (S11 to S13,..., S41 to S43) having maximum amplitude shift amount as synchronizing symbols 121 to 124 for taking the synchronization of the symbols are preliminarily assigned, and each of the synchronizing symbols 121 to 124 of plural subcarriers SC 1 to SC 4 is dispersed and arranged within the communication slot 101 not so as overlap even part of the symbols with each other on a time base.
Inventors:
Akira Yoshida
Application Number:
JP32712093A
Publication Date:
February 18, 1998
Filing Date:
December 24, 1993
Export Citation:
Assignee:
NEC
International Classes:
H04L27/38; H04J4/00; H04L5/26; H04L7/08; (IPC1-7): H04J4/00; H04L5/26; H04L7/08; H04L27/38
Domestic Patent References:
| JPH05276132A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)