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Title:
SMALL HIGH-SPEED PER-PIN IC TEST SYSTEM (PER-PIN IC TEST SYSTEMS SUCH AS ANALOG IC, DIGITAL IC, MIXED IC, MEMORY IC AND LOGIC IC)
Document Type and Number:
Japanese Patent JP2004029010
Kind Code:
A
Abstract:

To provide a per-pin IC test system preventing the breakdown of a circuit and a component due to heat and improving MTBF (mean time between failures), which solves the problem that such a breakdown and deterioration of a circuit due to heat or the insufficient reliability of MTBF are generally caused by increasing the driving frequency of IC than before, thereby increasing the economic loss required for restoring to its original state.

(1) The waveform voltage is controlled by a coaxial switch, and a custom switch matrix comprising the coaxial switch, a coaxial attenuator and a coaxial amplifier integrated with each other and its driver using an installed controller to prevent the "deterioration and breakdown" of components including a circuit board and a wiring of the per-pin IC test system due to "heat," thereby realizing the improvement of the reliability (MTBF) of the per-pin test system, the improvement of economic efficiency thereof, the reduction in cost, size and power consumption thereof, and the speeding up thereof. (2) The functions of phase controllers of the custom matrix and the line lengths of all the wirings are equalized, and a wiring form is employed in a wiring protective box, thereby dealing with the phase problems of the per-pin IC test system.


Inventors:
KOBAYASHI DAISUKE
Application Number:
JP2003141134A
Publication Date:
January 29, 2004
Filing Date:
April 14, 2003
Export Citation:
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Assignee:
KOBAYASHI DAISUKE
International Classes:
G01R31/28; (IPC1-7): G01R31/28