Title:
SOI AND CONFIGURATION METHOD THEREFOR
Document Type and Number:
Japanese Patent JPH06236976
Kind Code:
A
Abstract:
PURPOSE: To eliminate silicon mixture in a silicon oxide layer by forming a sacrificial layer of a predetermined thickness on a wafer surface, arranging ions in a predetermined depth under the surface of the wafer by ion-implantation and then conducting annealing. CONSTITUTION: First, a sacrificial layer 12 of a predetermined thickness is formed on the surface of a semiconductor wafer 10. Next, the surface of the wafer 10 is subjected to ion bombardment by ions 16 accelerated in the implantation step. When the ions 16 collide with the surface of the sacrificial layer 12, a sacrificial layer 10 is gradually sputtered by the ion bombardment and thereby removed. Therefore, since the thickness of the sacrificial layer 12 is reduced gradually, a peak concentration of implanted ions 18 is given at almost a constant interval from the surface of the wafer 10, and thereby the wafer 10 isolated with respect to a surface silicon layer 20 and a bulk silicon layer 22 by the implanted ions 18. When annealing is conducted after the ion- implantation, the excess oxygen in the surface silicon layer 20 diffuses to the outside from the silicon during the annealing. Thus a continuous embedded layer of an oxide film layer 24 of the chemical theory is formed by the reaction of implanted oxygen ions 18 and silicon.
Inventors:
KEISU EI JIYOINAA
MOHAMETSUDO KAMARU ERU GOAA
HARORUDO EICHI HOSATSUKU
MOHAMETSUDO KAMARU ERU GOAA
HARORUDO EICHI HOSATSUKU
Application Number:
JP26661693A
Publication Date:
August 23, 1994
Filing Date:
October 25, 1993
Export Citation:
Assignee:
TEXAS INSTRUMENTS INC
International Classes:
H01L21/02; H01L21/265; H01L21/76; H01L21/762; H01L27/00; H01L27/12; (IPC1-7): H01L27/12; H01L21/265; H01L21/76; H01L27/00
Attorney, Agent or Firm:
Akira Asamura (3 outside)