Title:
SYNCHRONIZATION DETECTING CIRCUIT
Document Type and Number:
Japanese Patent JP3151865
Kind Code:
B2
Abstract:
PURPOSE: To detect synchronization/non-synchronization of a phase locked loop by a comparatively simple circuit configuration, and also, to facilitate its design by combining theoretically an input signal, an output signal of a voltage control oscillating circuit, and their delay signal, in the phase locked loop circuit constituted of a phase comparing circuit, a loop filter and the voltage control oscillating circuit.
CONSTITUTION: Logic circuits (NAND 26-29) output a set signal and a reset signal by combining theoretically an input signal 5, its delay signal 9, an output signal 6 of a voltage control oscillating circuit 3, and its delay signal 10. By these set signals and reset signals, an S/R flip-flop 11 is driven, and a detection output of synchronization/non-synchronization is obtained.
Inventors:
Takashi Fujii
Application Number:
JP18601491A
Publication Date:
April 03, 2001
Filing Date:
July 25, 1991
Export Citation:
Assignee:
NEC
International Classes:
H03L7/095; (IPC1-7): H03L7/095
Domestic Patent References:
| JP1109969A | ||||
| JP2159120A | ||||
| JP6461119A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)