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Title:
SOLIDIFICATION RECORDER DEVICE
Document Type and Number:
Japanese Patent JPS6111988
Kind Code:
A
Abstract:

PURPOSE: To reduce memory capacity and to contribute recording and reproducing for a long term of hours by preventings data from being written in memory in the period of non-signal.

CONSTITUTION: A data comparator 22 is constituted in such a way that when either an shift register circuit 15 or 16 fetched compeletely digitized data of eight bits, namely, a bit block signal goes to L level, the result obtained by comparing output data from both shift register circuits 15 and 16 is unilized as normal data. This means that in case of non-signal state, digitized data outputted from an A/D conerter circuit 13 keeps L level. Accordingly, when both data are discriminated to be coincident by the data comparator 22, it is judged to be the non-signal stae, and an IC memory 20 will not be brought into the writable state. When data reading from the IC memory 20 is resumed, marker data is outputted again, and therefore the non-signal period is repeated at reproduction.


Inventors:
KOBAYASHI ISAO
NISHIZONO MINORU
Application Number:
JP13169584A
Publication Date:
January 20, 1986
Filing Date:
June 26, 1984
Export Citation:
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Assignee:
TOSHIBA KK
International Classes:
G11C7/00; G06F12/04; (IPC1-7): G11C7/00
Domestic Patent References:
JPS58106635A1983-06-25
Attorney, Agent or Firm:
Takehiko Suzue