Title:
SORTING METHOD FOR IC CHIPS
Document Type and Number:
Japanese Patent JPS5817632
Kind Code:
A
Abstract:
PURPOSE:To minimize the error of sorting IC chips by sequentially sorting the chips based on the test result of a wafer map while synchronizing with the IC marked with the marking information of the wafer map. CONSTITUTION:At the testing time, the movement of a tester on a wafer 1 is performed, for example, by 7 in a drawing. The head IC5 of each row is marked. Simultaneously, marking information M is recorded on the wafer map. The ICs in the same row are sequentially tested, and the test results[P (proper), F (failure)]are sequentially recorded on the wafer map. At the sorting time, the wafers are cut and separated into IC chips. Thereafter, at the time of sorting the IC chips, the sorter is moved as by 7 in the drawing similarly to the testing time. When the sorter detects the marked IC chip 5, the position of the chip and the marking information on the wafer map are corresponded to with each other perform synchronizing.
Inventors:
IIZUKA TSUNEO
Application Number:
JP11590481A
Publication Date:
February 01, 1983
Filing Date:
July 24, 1981
Export Citation:
Assignee:
FUJITSU LTD
International Classes:
H01L21/66; H01L23/544; (IPC1-7): H01L21/66
Domestic Patent References:
| JPS5389676A | 1978-08-07 |
Attorney, Agent or Firm:
Koshiro Matsuoka