Title:
ソースフォロア回路および液晶表示装置の駆動装置
Document Type and Number:
Japanese Patent JP4252855
Kind Code:
B2
Abstract:
When a set signal goes high, a gate-source voltage is stored by an input capacitor such that an NMOS transistor maintains a source potential at a drain current. Next, when a set signal goes low and a write signal goes high, the NMOS transistor performs a source-follower operation and enters a stable state while charging a load capacitor. At timing when writing into the load capacitor is finished, the set signal and the write signal are put into low states. By doing this, the writing voltage is stored by the load capacitor. At the same time, current sources are forcibly turned off and the flow of a very small amount of bias current completely stops so that no power is consumed.
Inventors:
Tatsumi Fuji
Ken Kawabata
Ken Kawabata
Application Number:
JP2003195213A
Publication Date:
April 08, 2009
Filing Date:
July 10, 2003
Export Citation:
Assignee:
ALPS ELECTRIC CO.,LTD.
International Classes:
G02F1/133; H03F3/50; G09G3/20; G09G3/36; H03F1/02; H03F3/00
Domestic Patent References:
| JP11073165A | ||||
| JP2002057537A | ||||
| JP3139908A | ||||
| JP3219713A | ||||
| JP63038312A |
Attorney, Agent or Firm:
Sumio Tanai
Masatake Shiga
Tadashi Takahashi
Hideyuki Sugiura
Suzuki Mitsuyoshi
Yasuhiko Murayama
Tadao Takashiba
Masatake Shiga
Tadashi Takahashi
Hideyuki Sugiura
Suzuki Mitsuyoshi
Yasuhiko Murayama
Tadao Takashiba