PURPOSE: To suppress the operating speed of the conversion circuit to a signal speed or below after the speed conversion by multiplexing a signal subject to serial parallel conversion at once and applying speed conversion to the multiplexed signal.

CONSTITUTION: Serial parallel converters 101-103 convert an inputted one string into n-train signals. Let the signal speed of the input signal be f0, then the signal speed of outputs of the converters 101-103 is f0/n. Since outputs of all the serial parallel converters are inputted to a multiplexer circuit 201, number of lines for the input signal is m.n lines. Then the circuit 201 applies multiplexing for n trains of output signals of m-sets of the serial parallel converters to output the n-train signals whose signal speed is m.f0/n. A PLL circuit 301 synchronizes a clock before speed conversion with a clock after speed conversion and outputs the clock after the speed conversion whose frequency is m.f0/n synchronously with the input clock from an output terminal 41. The circuit 201 is a circuit operated at a fastest speed in the speed conversion circuits and the operating speed is equal to the signal speed after the speed conversion.