PURPOSE: To reduce a time lag with simple circuit constitution by making input- side digital multiplexing circuits differ in time lag and then by changing them over.

CONSTITUTION: Input-side digital multiplexing circuit 11 is given different time lags by delay circuits 21 and 22 and connected to selecting circuit 23 respectively. When the multiplicity of circuit 11 is higher than that of output-side digital multiplexing circuit 12, circuit 23 selects circuit 11 with no time lag and sends its output to it according to a switching signal applied to terminal 25 and then sends the output to other circuits from the least-delay circuit successively by changing them over. Memory circuit 24 fetches the output by clock pulses, corresponding to circuit 12, applied to terminal 26 and outputs them onto circuit 12. When the multiplicity of circuit 11 is greater than that of circuit 12, on the other hand, circuit 23 changes the circuits over from the greatest-delay one in sequence. Thus, desired speed conversion can be performed. Consequently, delay is provided by only circuits 21 and 22 and the extremely simple circuit constitution can reduce the delay.