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Title:
SPEED DETECTING CIRCUIT
Document Type and Number:
Japanese Patent JPS5913957
Kind Code:
A
Abstract:

PURPOSE: To simplify circuit constitution and to detect a speed precisely in a short time by employing the constitution of a counter, register, and arithmetic circuit which is suitable for LSI implementation.

CONSTITUTION: A counted value T1 corresponding to the interval between a position pulse S1 and a reference pulse R1 is set in a B register 63. When a reference TP is generated, the counted value of a timer counter 62 is set in the B register 63. This counted value T2 corresponds to the interval between a position pulse S4 and a reference pulse R2. The arithmetic circuit 64 reads the counted value T2 out of the B register 63 and solves the 1st equation by using the preceding counted value T1 and a known period T0 to calculate an input necessary time T. Further, the arithmetic circuit 64 reads the number N of position pulses PP in the period between the reference pulses R1 and R2 out of an A register 61, and solves the 2nd equation to obtain speed information V.


Inventors:
SAKANO TETSUROU
Application Number:
JP12328482A
Publication Date:
January 24, 1984
Filing Date:
July 15, 1982
Export Citation:
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Assignee:
FUJITSU FANUC LTD
International Classes:
G05D13/62; G01P3/489; G01R23/10; G05B19/23; H02P29/00; (IPC1-7): G01P3/489; G01R23/10; G05D13/62; H02P5/00
Domestic Patent References:
JPS5748664A1982-03-20
JPS5623529A1981-03-05
Attorney, Agent or Firm:
Minoru Tsuji



 
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