To provide an SSCG circuit including a new fractional PLL circuit eliminating a principle of operation of changing the frequency division ratio of a frequency divider which reduces jitter in an output clock signal.

The SSCG circuit includes a phase frequency comparator 1, a charge pump 2, a loop filter, a voltage-controlled oscillator 4, a phase controller 5, and a phase selection circuit 6. The phase selection circuit 6 selects any one of equally divided phases of one clock period of an output clock signal vco_ck from the voltage-controlled oscillator 4, generates a phase shift clock signal pi_out having a leading edge in the selected phase, and feeds it as a feedback signal to the phase frequency comparator 1. The phase controller 5 controls the phase selection circuit 6 such that the period of the phase shift clock signal pi_out is shifted by a predetermined first phase shift from the period of the output clock signal vco_ck and that a second phase shift periodically changing within a predetermined range is added to the first phase shift.