To enhance a noise margin without having an adverse effect to write-in performance by providing a pass transistor in write-in.

This SRAM 10 is composed by cross-joining a first inverter 12 with a second inverter 18, and first, second write-in pass transistors 32, 34 are connected to first, second pass transistors 24, 25 respectively in parallel. Then, a more narrow width is selected for the first, second pass transistors 24, 25, and the write-in pass transistors are kept to off-state during read-in, and a high beta ratio is attained, and a static noise margin for its cell is enhanced. Further, by designing the write-in pass transistor with a more wider width, and by turning on both of the pass transistors and the write-in pass transistors during the write-in, the beta ratio of the cell is reduced remarkably, and the write-in to the cell is facilitated further.