Title:
SRAM HAVING DOUBLE VERTICAL CHANNELS AND MANUFACTURE THEREOF
Document Type and Number:
Japanese Patent JP3220813
Kind Code:
B2
Abstract:
PURPOSE: To manufacture an SRAM which enables high integration by a method, wherein the channel region of the transistor is formed so as to have a double vertical structure.
CONSTITUTION: A grounding electrode 7 is connected to a ground GND, 3rd impurity regions 6 and 6a are connected to bit lines BL and BL respectively, 2nd gate electrodes 9 and 9a are connected to a work line W/L and load resistors 13 and 13a and 1st gate electrodes 8 and 8a are connected to an electrode VDD. A region 14 is an isolation region for isolating the transistor from a cell, for instance an oxide film which is formed from the surfaces of 2nd epitaxial layers 5 and 5a to the insides of 1st epitaxial layers 3 and 3a. Second impurity regions 4 and 4a are used as common source/drain region of the transistors. The 1st epitaxial layers 3 and 3a and the 2nd epitaxial layers 5 and 5a, which are positioned vertically between a 1st impurity region 2, the 2nd impurity regions 4 and 4a and the 3rd impurity regions 6 and 6a function as the double vertical channels of the transistors.
Inventors:
Seo Kyu Li
Application Number:
JP13967492A
Publication Date:
October 22, 2001
Filing Date:
May 06, 1992
Export Citation:
Assignee:
Ergi Semicon Company Limited
International Classes:
H01L21/8244; H01L27/11; (IPC1-7): H01L21/8244; H01L27/11
Domestic Patent References:
| JP60239052A | ||||
| JP2501251A |
Attorney, Agent or Firm:
Masaki Yamakawa