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Title:
STACK AREA MANAGING SYSTEM
Document Type and Number:
Japanese Patent JPH04188326
Kind Code:
A
Abstract:

PURPOSE: To reduce the number of times of data transfer, and to attain high- speed processing by invalidating the entry of an exclusive cache for a stack area corresponding to the stack area having become useless after return from routine.

CONSTITUTION: When an instruction executing means 17 issues a read-in request to a stack area accessing means 12, the stack area accessing means 12 inquires whether requested data exists in the exclusive cache for the stack area or not of a cache control means 15, and the cache control means 15 decides whether the requested data exists in the exclusive cache for the stack area or not. Then, the routine after the return invalidates the entry of the exclusive cache 16 for the stack area corresponding to the stack area 21 having become useless because of the return. Thus, the number of times of the data transfer between a CPU 1 and a main storage device 2 can be reduced, and further increase of processing speed can be attained because of the shortening of processing time.


Inventors:
TAMARU MASAAKI
Application Number:
JP31886090A
Publication Date:
July 06, 1992
Filing Date:
November 22, 1990
Export Citation:
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Assignee:
NEC CORP
International Classes:
G06F12/08; G06F9/42; (IPC1-7): G06F9/42; G06F12/08
Attorney, Agent or Firm:
Sakai Hiromi



 
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