Title:
STACK CELL MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
Document Type and Number:
Japanese Patent JPH1093053
Kind Code:
A
Abstract:
To increase integration density of a DRAM, while suppressing generation of a soft error.
A cylindrical spacer region 28 is provided on a semiconductor region 10, and the spacer region 28 surrounds a memory node contact region 14 in such a manner as to expose its contact region. A conductive memory node 22 surrounds the outside, inside and upper parts of the spacer region 28, in such a manner as to be electrically connected to the memory node contact region 14 and that a conductive plate 26 is capacitively connected to the memory node 22.
Inventors:
MOROI MASAYUKI
HIROSE KIYOMI
BOKU KATSUJI
HIROSE KIYOMI
BOKU KATSUJI
Application Number:
JP22538997A
Publication Date:
April 10, 1998
Filing Date:
August 21, 1997
Export Citation:
Assignee:
TEXAS INSTRUMENTS INC
International Classes:
H01L27/04; H01L21/822; H01L21/8242; H01L27/108; (IPC1-7): H01L27/108; H01L21/8242; H01L27/04; H01L21/822
Attorney, Agent or Firm:
Akira Asamura (3 outside)