Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
STACK LENGTH DESIGNATING SYSTEM
Document Type and Number:
Japanese Patent JP59117641
Kind Code:
A
Abstract:

PURPOSE: To reduce the burden of a program, by defining a stack length with a data designated by the program at the jump instruction execution and defining a fixed value if the program does not designate with the data and designating the stack length by the program only when it is required.

CONSTITUTION: When the control is jumped to a subroutine B by a jump instruction of a main program A, contents of address 400 are read out to a stack length register 2, and a stack length decoder 3 outputs "no signal", and contents (64)D of the register 2 are outputted by a selecting circuit 5 and are added to value (700)D of a stack point register 6 by an adding circuit 7, and contents of the register 6 are updated to (764)D. Next, when the control is jumped to a subroutine C, contents (32)D of a fixed data generating circuit 4 are selected in the input of the selecting circuit 5 because contents of address 500 are (0)D, and contents (32)D of the circuit 4 are added to value (764)D of the register 6 by the adding circuit 7, and contents of the register 6 are updated to (796)D.


Inventors:
Furukawa, Kazuo
Yamada, Shigeki
Matsushita, Masayoshi
Sakata, Hironobu
Sakamoto, Yasuhiko
Application Number:
JP1982000226262
Publication Date:
July 07, 1984
Filing Date:
December 24, 1982
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
HITACHI LTDNIPPON TELEGR & TELEPH CORP
OKI ELECTRIC IND CO LTD
NEC CORP
FUJITSU LTD
International Classes:
G06F9/46; G06F9/42; G06F9/48; G06F9/46; G06F9/40; (IPC1-7): G06F9/46