Title:
セルフタイミング回路を有するスタティックメモリ
Document Type and Number:
Japanese Patent JP4339532
Kind Code:
B2
Abstract:
A static memory including a memory cell array having word lines, bit line pairs, and memory cells, each having a pair of nodes holding opposite levels; includes a dummy circuit disposed along the memory cell array, having a dummy word line, a dummy bit line pair, a self-timing dummy memory cell connected to the dummy word and bit lines and having a pair of nodes holding opposite levels, and load dummy memory cells connected to the dummy bit line pair; and a timing control circuit for detecting a voltage change of the dummy bit line pair to generate a start signal to a sense amplifier. The pair of nodes of the self-timing dummy memory cell are fixed to a first status, and the pair of nodes of the load dummy memory cell are fixed to a second status opposite to first status.
Inventors:
Go Kodama
Application Number:
JP2001224922A
Publication Date:
October 07, 2009
Filing Date:
July 25, 2001
Export Citation:
Assignee:
Fujitsu Microelectronics Limited
International Classes:
G11C11/417; G11C11/41; G11C11/413; G11C11/419
Domestic Patent References:
| JP5504648A | ||||
| JP7006182A | ||||
| JP2001110187A | ||||
| JP5198175A | ||||
| JP2000516008A | ||||
| JP10021688A |
Attorney, Agent or Firm:
Kenji Doi
Hayashi Tsunetoku
Hayashi Tsunetoku
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